Storage devices based on flash memories have become very attractive in the last years; for example, they are commonly used as mass memories (also known as solid-state mass memories) in several data processing systems. These storage devices are compact, robust and with low power consumption; therefore, they may be advantageous, especially in portable systems (such as mobile telephones), which are typically supplied by batteries.
Typically, flash memories used to implement the above-mentioned storage devices can be erased only in blocks having a relatively large size (for example, 16-32 Kbytes). Therefore, once data has been written into the flash memory, this data cannot be updated unless the corresponding whole block is erased. In order to emulate operation of a random access device (such as a standard hard-disk), a translation layer is provided on top of the flash memory. The translation layer manages any update of the data stored in the flash memory by writing a new version thereof in a different area of the flash memory, and at the same time updating corresponding mapping information.
A problem with some storage devices based on flash memories is that the number of times each block can be erased is intrinsically limited, for example, on the order of 100,000-300,000 times. Indeed, every erasing of the block physically wears its memory cells. As a result, as time goes on more time is required to erase the memory cells, sporadic faults may appear when they are programmed, and the capability of distinguishing between different conditions (e.g., storing a “0” or a “1”) thereof lessens; in the end, the block may entirely lose the ability of being erased, thereby becoming unusable (or bad). This limited endurance to the erasures of the blocks reduces the lifetime of the storage devices.
In order to alleviate the above-described problem, wear leveling techniques have been proposed. The wear leveling techniques are aimed at distributing the number of erasures of the blocks uniformly throughout the whole flash memory. In this way, all the blocks should approach the number of their allowable erasures; as a result, the lifetime of the memory device theoretical tends towards its maximum value.
For example, an approach that has been proposed is of selecting the blocks to be used for writing data with a random algorithm; statistically, the blocks should then be erased with a similar frequency.
As a further improvement, US-A-2006/0155917 (the entire disclosure of which is herein incorporated by reference) discloses a solution that is based on a table storing the number of erasures of each block of the flash memory; the table is used to create a list, which orders the erased blocks (being available to be used for writing data) according to their number of erasures. In this way, whenever an erased block must be used for writing data, it is possible to select the one with the lowest number of erasures; the selected block is likely to be erased again later on, so as to increase the uniformity of the distribution of the erasures.
However, the solutions known in the art may not be completely satisfactory in some applications. Indeed, the available wear-leveling techniques are often ineffective in obtaining an actual uniform distribution of the erasures of the blocks in the flash memory.
Therefore, in many practical situations it may be that the erasures concentrate on some blocks only. As a result, those blocks may become unusable in a relatively short time, while other blocks are subject to a far lower number of erasures. Unfortunately, this may have detrimental effect on the lifetime of the whole memory device.